Many open-source projects target existing, commercial hardware without official support from the hardware vendor. Some of the most famous examples include Linux and the GCC compiler; which all started as third party projects.
These days both of these projects see significant support from large hardware companies and are used as the official tooling for many widely sold products. Both now see significant first-party contributions from hardware vendors.
Over the last three years, I have been part of the community developing open source tooling for field-programmable gate arrays (FPGAs). These are programmable logic chips with great potential for “post Moore’s law” reconfigurable computing with many promising applications from consumer devices to datacentres.
In general, FPGA companies have not published the low-level details of the devices – unlike CPUs, where the instruction set is almost always public. The expectation is that everyone uses the closed-source vendor-specific toolchain provided.
As a result, to develop a complete open-source flow from design to device programming for most FPGAs, the low-level “bitstream” details must be documented by creating a large number of designs using the vendor-provided tools and examining the output. Claire Wolf did this for the Lattice iCE40 FPGAs five years ago in Project Icestorm. Subsequently, I created open-source documentation for their larger ECP5 FPGAs.
In both cases, combined with the low cost and simplicity of these Lattice parts, these projects have led to popular open-source flows for both devices. From this has sprung a number of open source development boards such as the myStorm BlackIce, icebreaker and ULX3S.
Vendors are now acknowledging the importance of open source
Whilst downloading a newly released Lattice SDK, I found there was a new clause in the license agreement prohibiting this bitstream documentation. Fortunately, this SDK doesn’t directly affect any of the currently supported devices, but it would have become problematic if all their tools sport this license in the future:
e. Licensee shall not distribute, copy, transfer, lend, incorporate, modify, use or sublicense the Software or any Modules for any purpose except as expressly provided herein or as otherwise permitted under relevant law, or in advance by Lattice in writing. In particular, no right is granted hereunder … or (3) for reverse engineering a bit stream format or other signaling protocol of any Lattice Semiconductor Corporation programmable logic device.
Thanks to lobbying from the community, it is great to see that Lattice has shown commitment to open source by promptly removing the clause after being contacted about it, going as far as to publish a message of appreciation for the open-source community on Twitter:
Thanks for pointing out a new bitstream usage restriction in the Lattice Propel license. It is not our intent to hinder open source tools. See https://bit.ly/3eUM3OD re an updated license. We are excited with the open source community’s FPGA achievements and their potential. https://twitter.com/latticesemi/status/1269115302140231682
This is a risk that Lattice has taken, but it is one that resonates well with the open-source toolchain developers and will hopefully yield good results for them in the future. It also shows the power of a strong open source community to achieve good results from companies and the growing awareness for the open source.
I hope that as time progresses we see more support for open source tools from FPGA vendors, perhaps even reaching a similar point to established open -source software tooling.
David Shah is a self-employed developer working on nextpnr, the open source FPGA place-and-route tool. His previous work also includes Project Trellis, open source bitstream documentation for the Lattice ECP5 FPGAs.