risc-v


Adding an Instruction to the GNU Assembler

Binutils is a huge piece of code and new users can often feel lost and out of their depth when navigating it alone. To help ease the shock, in this post we’ll look at the very simplest step of adding a new basic instruction to an already defined extension and how to add a corresponding GNU Assembler (GAS) test.

While the examples and files given are all RISC-V specific, the information is transferable to other architecture ports, however tables and structures may differ. More information can be found through the binutils project page.

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Inaugural London RISC-V Meetup – July 2019

At this evening meeting in London on Monday 22 July we have three talks with speakers looking at open source in the RISC-V Ecosystems. This is our fifth meeting since 2014 on the subject of RISC-V, but the first to be held jointly with the RISC-V Foundation as part of their global meetup program

This is a joint meeting with the UK Open Source Hardware User Group.

Full details, including how to register are on the events page.


Machines and systems of past, present, future – January 2019

To start off the year, we have a series of talks around the theme of Acorn computers, RISC OS, RISC-V toolchain.

  • Brief history of Unix-like operating systems on Acorn hardware – Stephen Borrill
  • RISC OS : What’s Next – Richard Brown
  • Embedded FreeBSD on a five-core RISC-V processor using LLVM – Jeremy Bennett
  • Buildroot for RISC-V (Using Buildroot to create embedded Linux systems for 64-bit RISC-V) – Mark Corbin

For those unable to be present in person the meeting will be recorded and also live streamed over GoToWebinar:

https://attendee.gotowebinar.com/register/7524829278273993474

GoToMeeting system check:
https://link.gotomeeting.com/system-check

For more details and registration see the page on Eventbrite.