Adding an Instruction to the GNU Assembler

Binutils is a huge piece of code and new users can often feel lost and out of their depth when navigating it alone. To help ease the shock, in this post we’ll look at the very simplest step of adding a new basic instruction to an already defined extension and how to add a corresponding GNU Assembler (GAS) test.

While the examples and files given are all RISC-V specific, the information is transferable to other architecture ports, however tables and structures may differ. More information can be found through the binutils project page.


FPGA vendor Lattice acknowledges value of open source community

Many open-source projects target existing, commercial hardware without official support from the hardware vendor. Some of the most famous examples include Linux and the GCC compiler; which all started as third party projects.

These days both of these projects see significant support from large hardware companies and are used as the official tooling for many widely sold products. Both now see significant first-party contributions from hardware vendors.

Over the last three years, I have been part of the community developing open source tooling for field-programmable gate arrays (FPGAs). These are programmable logic chips with great potential for “post Moore’s law” reconfigurable computing with many promising applications from consumer devices to datacentres.

In general, FPGA companies have not published the low-level details of the devices – unlike CPUs, where the instruction set is almost always public. The expectation is that everyone uses the closed-source vendor-specific toolchain provided.

As a result, to develop a complete open-source flow from design to device programming for most FPGAs, the low-level “bitstream” details must be documented by creating a large number of designs using the vendor-provided tools and examining the output. Claire Wolf did this for the Lattice iCE40 FPGAs five years ago in Project Icestorm. Subsequently, I created open-source documentation for their larger ECP5 FPGAs.

In both cases, combined with the low cost and simplicity of these Lattice parts, these projects have led to popular open-source flows for both devices. From this has sprung a number of open source development boards such as the myStorm BlackIce, icebreaker and ULX3S.

Vendors are now acknowledging the importance of open source

Whilst downloading a newly released Lattice SDK, I found there was a new clause in the license agreement prohibiting this bitstream documentation. Fortunately, this SDK doesn’t directly affect any of the currently supported devices, but it would have become problematic if all their tools sport this license in the future:

e. Licensee shall not distribute, copy, transfer, lend, incorporate, modify, use or sublicense the Software or any Modules for any purpose except as expressly provided herein or as otherwise permitted under relevant law, or in advance by Lattice in writing. In particular, no right is granted hereunder … or (3) for reverse engineering a bit stream format or other signaling protocol of any Lattice Semiconductor Corporation programmable logic device.

Thanks to lobbying from the community, it is great to see that Lattice has shown commitment to open source by promptly removing the clause after being contacted about it, going as far as to publish a message of appreciation for the open-source community on Twitter:

Thanks for pointing out a new bitstream usage restriction in the Lattice Propel license. It is not our intent to hinder open source tools. See https://bit.ly/3eUM3OD re an updated license. We are excited with the open source community’s FPGA achievements and their potential.


This is a risk that Lattice has taken, but it is one that resonates well with the open-source toolchain developers and will hopefully yield good results for them in the future. It also shows the power of a strong open source community to achieve good results from companies and the growing awareness for the open source.

I hope that as time progresses we see more support for open source tools from FPGA vendors, perhaps even reaching a similar point to established open -source software tooling.

David Shah is a self-employed developer working on nextpnr, the open source FPGA place-and-route tool. His previous work also includes Project Trellis, open source bitstream documentation for the Lattice ECP5 FPGAs.

Inaugural London RISC-V Meetup – July 2019

At this evening meeting in London on Monday 22 July we have three talks with speakers looking at open source in the RISC-V Ecosystems. This is our fifth meeting since 2014 on the subject of RISC-V, but the first to be held jointly with the RISC-V Foundation as part of their global meetup program

This is a joint meeting with the UK Open Source Hardware User Group.

Full details, including how to register are on the events page.

What’s New in Cryptography & Security – July 2019

At this evening meeting in London on Thursday 18 July we have three talks with speakers looking at what’s new in cryptography and security. We last looked at this topic in April 2015, and in the intervening time the maker movement has evolved often, but not always, for the better.

This is a joint meeting with the UK Open Source Hardware User Group.

Christopher Wade of Pen Test Partners will present an analysis of common weaknesses in IOT devices.

Glyn Wintle, CTO at dxwcyber, will explain why you should choose Open Source crypto.

Alec Muffett of the Open Rights Group and Deliveroo will deliver a talk on why and how you should start using Onion Networking.

Full details, including how to register are on the events page.

Women in Open Source – May 2019

At this evening meeting in London on Thursday 16 May we’ll be welcoming three women, all of whom are pursuing a career in open source.  This is a joint meeting with BCS Women and the UK Open Source Hardware User Group.

Rain Ashford of Goldsmiths University will talk about Prototyping wearables with open source

Pietra F T Madio, a sixth form student at Brockenhurst College will talk about Starting out in open source

Prof Cornelia Boldyreff of the University of Greenwich, past Chair of the BCS OSSG and BCS Council member will talk about A more inclusive way of looking at open source projects.

For full details, including how to register are on the events page.

Open Source FPGA Hardware and Tooling Past, Present and Future – March 2019

In this meeting, held on 21 March 2019 at BCS London, we heard from two speakers on the state of open source FPGA technology.

Once upon a time we could only use proprietary tools and development boards supplied by FPGA vendors, This all changed in 2016 with the advent of the IceStorm opensource toolchain combined with open Hardware like the myStorm board. With the 2nd generation of tools and hardware sophisticated FPGA features are opening exciting avenues for ‘Opensource all the way down’, we hope to provide an update and crystal ball on where some of this could be leading to.

Tools: past to present

David Shah looks at where we have come from with the IceStorm toochain, and looks at how this has devloped recently and expanded Ice40 Lattice support to include new lower power, lower cost, reduced pincount FPGAs to inlcude their Ultra & Ultra Plus range.

Hardware: past to present

Alan Wood talks about the journey through the early history of OpenSource FPGA open hardware from IcoBoard through myStorm too recent UltraPlus offerings recently made available.

Tools: present to future

Icestorm was aimed at a narrow family of Ice40 FPGAS, the new Symbiflow family of tools expands the opensource tooling exponetially. David Shah takes a look at NextPNR which lies at the heart of the toolset and deals with specific FPGA family functionality, in particular he concentrates on the Lattice ECP5 family support he has developed with Project Trellis as part of NextPNR and the recent 1.0 version supporting this new family and high end FPGA features.

Hardware: present to future

What comes next for opensource FPGA hardware, after the success of tinyFPGA and myStorm we are begining to see ECP5 opensource hardware emerging first with Radiona’s ULX3S and being followed up by offerings from both tinyFPGA and myStorm dev board stables, with new hardware comes new features building on NextPNRs tooling like DSP, SerDES IO Gearing and DDR memory etc, Alanplots the course for these new powerfull opesource development boards…


Time permitting we can show some of what’s possible with the new tools in a brave new ‘Opensource all the way down’ world.

David Shah, @fpga_dave, is a engineer at Symbiotic EDA and a Electronic and Information Engineering student at Imperial College London. He entered the world of open source FPGAs by extending Project Icestorm, the iCE40 bitstream documentation project, to include the newer iCE40 UltraPlus FPGAs. As well developing Project Trellis, he has been involved in the development of a new open source FPGA place-and-route tool, nextpnr.

Alan Wood, @folknology, has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation, biotec diagnostics and designing FPGA devboards. His current research is focused on machine learning for embedded automation using FPGAs. He is a long term advocate of open source communities, a moderator (aka Folknology) for xCORE, the co-founder of myStorm open hardware FPGA community, as well as a co-founder of Surrey and Hampshire Makerspace.

Open Source Security – February 2019

Our second meeting of the year is an evening on the theme of security and hosted by Cheltenham and Gloucester BCS at the University of Gloucester. We have two talks

  • SCARV: a side-channel hardened RISC-V platform by Dr Daniel Page of the University of Bristol.
  • Open source tools and processes for secure IoT development by Dr Jeremy Bennett of Embecosm.

Full details can be found on the events page.

The evening is free to the attend. For those who cannot be present, the talks will be recorded, but we regret that on this occasion we are unable to offer live streaming.