Inaugural London RISC-V meetup

July 22, 2019 @ 5:30 pm – 8:00 pm
IET London, Watson-Watt Room
2 Savoy Pl
London WC2R 0BL
Dr Jeremy Bennett
+44 1590 610184

This was the inaugural London meetup for the RISC-V community, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group.  As with the other UK meetups, we provided an opportunity to share the latest ideas around the RISC-V ecosystem, combined with plenty of time for networking. However unlike other meetups, the London meetup had a specific focus on the open source aspects of RISC-V.

Note. Because of the impending BCS London office move, the venue was moved to the Watson-Watt room at the IET in Savoy Place, 4 minutes walk away.

At this evening meeting we had three talks on the OpenHW group, the LowRISC project and the XCrypt instruction set extension.  The talks are now available on our YouTube channel

Eventbrite - Open Source SG - London RISC-V Meetup

Tea/coffee will be served from 5:30pm, with talks starting at 6:00pm. Each talk will last 20-30 minutes and include plenty of time for questions, after which there will be opportunity to network both in the IET  and later at the Coal Hole pub over the road.

We shall be livestreaming and recording the talks for later posting on YouTube via GoToWebinar. To register for live streaming visit:

After registering, you will receive a confirmation email containing information about joining the webinar.

The LowRISC project

Alex Bradbury, @asbradbury

Alex talked about lowRISC, a non-profit community interest company, using collaborative engineering to develop and maintain open source silicon designs and tools.  Their expertise includes processor and SoC design, with a particular focus on hardware security, design verification, RISC-V tools, and the LLVM compiler.

Alex Bradbury is a Co-founder and Director of the lowRISC project. You may also be familiar with his LLVM work, and the LLVM Weekly newsletter. 

Open Source Processor IP for High Volume Production – the CORE-V Family
of RISC-V cores

Rick O’Connor, @rickoco

This session provides a brief overview of the RISC-V instruction set architecture and to describe the CORE-V family of open-source cores that implement the RISC-V ISA.  RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration.  Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

CORE-V is a series of RISC-V based open-source processor cores with associated processor subsystem IP, tools and software for electronic system designers under the governance of the OpenHW Group.  The CORE-V family provides quality core IP in line with industry best practices in both silicon and FPGA optimized implementations.  These cores can be used to facilitate rapid design innovation and ensure effective
manufacturability of production SoCs.

Rick O’Connor is Executive Director of OpenHW

The XCrypt instruction set extension

Ben Marshall

Secure and efficient execution of cryptographic workloads is essential for any modern computer architecture. Particularly as more and more resource constrained devices need to communicate securely in potentially adversarial environments.  This talk will discuss some problems with the base RISC-V ISA from a cryptographic point of view, and how they can be improved.  Specifically we describe our work on XCrypto: a custom extension for general purpose cryptography, aimed at embedded RISC-V processors.

Ben Marshall is a Research Associate on the SCARV project.

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