RISC-V, RISC-V, RISC-V – London

Risk-VThe BCS OSSG and the OSHUG are hosting their next event on 23rd November 201718:00 – 21:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812-0.121733)

The event will be on the theme of RISC-V, an open ISA which started life at the University of California, Berkeley.

This event is free to attend for both BCS Members and non-members but booking is required. Places are limited; please book as soon as possible.

Bringing up cycle-accurate models of RISC-V cores

The openness of the RISC-V ISA has enabled the development of many open-source RISC-V cores with varying capabilities. Choosing an implementation that meets given requirements can be done to some extent by comparing specifications and other attributes of the cores, but any decision must be based on actual testing. Using Verilator to generate cycle-accurate models enables rapid development of testing platforms. This talk provides a report of our experience bringing up cycle-accurate models of two cores in particular, RI5CY from the PuLP project, and Clifford Wolf’s PicoRV32. For testing, a software ecosystem consisting of a compiler, binary utilities, debugger, and an interface between the model and debugger accompanies the Verilator model. To compare the cores, we used the GCC test suite and the RISC-V ISA test suite for measuring correctness, and the Bristol/Embecosm Embedded Benchmark Suite (BEEBS) to compare performance. All code and scripts used for the implementation are open-source, and can be re-used by others who wish to do similar exercises with other RISC-V cores.

Edward Jones has a background in parsing techniques and works at Embecosm on LLVM and GNU toolchains. He is also involved in research by Embecosm to investigate ways in which the software tool chain can reduce program energy consumption. Edward Jones is a Computer Science graduate of the University of Kent.

FreeBSD/RISC-V and Device Drivers

The FreeBSD port to RISC-V 64-bit ISA was added in January 2016. FreeBSD is the first operating system that officially supported RISC-V in the main repository. Since its introduction, support has evolved, RISC-V privileged architecture has updated a few times. The platform is maturing making it suitable for general, commercial, research and educational use. The GCC v7.0 target for RISC-V was officialy upstreamed and NVIDIA is planning to ship all of their GPUs with RISC-V coprocessor enabled in the future. Several companies have announced the start of RISC-V chip development and many universities are taking RISC-V as a target architecture for doing research. The world first RISC-V microcontroller-class board HiFive1 was released and we are getting closer to the first general purpose board to become available! This talk will describe the current status of FreeBSD/RISC-V, toolchain and supported simulators. The porting process as well as describing the latest changes made to FreeBSD in order to support the latest RISC-V privilege specification (v1.10). This includes enabling by default FDT support and drivers attachment change, SBI interface, compiler flags/built-in definition changes, support for updated BBL boot loader, RISC-V privilege levels, initial page tables build, page table entry flags and other changes. An overview of FreeBSD device drivers subsystem will also be covered describing the device frameworks, buses and kernel-interfaces that exists in FreeBSD (e.g. Newbus, cdevsw, bus_dma, SYSINIT, vt, sound, ifnet, spibus, etc), how to use and configure them and how to debug a device driver. This should answer the question: How to write device driver for FreeBSD/RISC-V?

Ruslan Bukin is a Research Associate at University of Cambridge Computer Laboratory. He has been a FreeBSD user since 2002 and src committer since 2013. His main interests and contributions to FreeBSD are related to computer architectures support, performance monitoring technologies support, hardware tracing technologies (Intel PT), devicedrivers, DMA engines and DMA frameworks, hardware security (Intel SGX, CHERI), heterogeneous computing. Ruslan is the lead developer of the FreeBSD/RISC-V project. He obtained a Computer Science degree in 2008 from Peoples’ Friendship University of Russia in Moscow

Talk #3 TBA

Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt.

Closing date for bookings is Tuesday 21st November 2017 at 11:30 pm. No more bookings will be taken after this date. For overseas delegates who wish to attend the event please note that BCS does not issue invitation letters


OSSG AGM, Reimagining EDSAC, NetBSD Updates, Semantic and Change Coupling of Software Classes – London 19/10/2017

The BCS OSSG is hosting its next event on 19th October 201718:00 – 21:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812-0.121733)

This event is free to attend for both BCS Members and non-members but booking is required. Places are limited; please book as soon as possible.

The meeting this month will start with the BCS OSSG AGM and this will be followed by a talk on recent and planned improvements to NetBSD, a report from Chip Hack EDSAC Challenge, and finally a talk on the interplay between semantic coupling and co-change of software.

BCS Open Source SG – AGM

All members of OSHUG are welcome to attend and OSHUG members are encouraged to put themselves forward to join the committee. In particular we would welcome anyone to join the event organizers who arrange the speakers for each month and the occasional all-day workshops. Currently we have Sevan Janiyan, @ndy Bennett and Andrew Back as event organizers on the committee.

Updates to the NetBSD operating system since OSHUG #57 & #58

NetBSDSince the workshops held earlier this year, numerous changes have been made to the NetBSD operating system to ensure future workshops are easier for users and work smoother from the outset. This talk will cover some of the improvements made so far and what’s currently in the works. From wrestling with the u-boot firmware to new tools included in the os and much more.

Sevan Janiyan is founder of Venture 37, which provides system administration & consultancy services. As a fan of operating systems and computers with different CPU architectures, in his spare time he maintains builds of open source software on a variety of systems featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube & OMRON LUNA-88K2 one day.

Reimagining EDSAC: The ChipHack experience

ChiphackChipHack is an occasional 2 day workshop introducing students and hobbyists to FPGA design. This year, ChipHack was sponsored by the BCS OSSG and Computer Conservation Society. To celebrate the 60th anniversary of the BCS, the workshop was extended by half a day and attempted to reimagine one of the earliest valve computers, EDSAC, designed by the BCS’ founding president, Prof Sir Maurice Wilkes.

Merry Bennett led the team putting together the technical content of the workshop. She will report back on what was achieved, from the three implementations of the computer, to the diverse reimagining of the original peripherals. The result is a legacy of lectures and videos, to allow anyone to run their own ChipHack course.

The Interplay between Semantic Coupling and Co-Change of software classes

During maintenance, developers must ensure that related entities are updated to be consistent with these changes. Studies in the static change impact analysis domain have identified that a combination of source code and lexical information outperforms using each one when adopted independently. The presentation has two aims: first, to compare the effectiveness of measuring semantic coupling of OO software classes using (i) simple identifier based techniques and (ii) the word corpora of the entire classes in a software system. Second, to empirically investigate the interplay between semantic and change coupling.

Dr Andrea Capiluppi joined the Department of Computer Science at Brunel University London (UK), as a Lecturer in Software Development in May2012. Between 2009 and 2012 he was at University of East London, working as a Senior Lecturer in Software Engineering. Before that, he worked as a Senior Lecturer and at University of Lincoln between 2006 and 2009. Andrea’s research and teaching interests focus on Software Evolution and Maintenance, as well as the construction, evaluation and maintenance of Social Networks. Andrea is mostly interested in the use of open technologies and in understanding how they can improve learning and teaching as well as the production of software and other artefacts.

After-event follow up

Update from Judith Jones (Embecosm) on behalf of the organisers: Following our recent successful Chip Hack EDSAC Challenge, sponsored by
the BCS, I am pleased to provide you with feedback, as follows:

Of 80 registrations for the Chip Hack EDSAC 2017 event, 67 people attended.  The event was designed to be a collaborative learning experience and brought together 3 expert silicon chip designers, 11 experienced people, 17 people with some experience and 36 complete beginners.  The legacy of the event is a body of materials available under open source licence to enable people to run their own Chip Hack EDSAC events in the future, thereby making silicon chip design accessible to the individual engineer, whether professional, hobbyist or student.  The technical materials are freely available through http://chiphack.org/, myStorm boards will be freely loaned through the BCS (stored at, and managed by, Embecosm) and recordings of the workshops and talks will be available, post-editing, through https://www.youtube.com/user/embecosm.  In addition, Andrew Back is producing a documentary with the working title Chip Hack EDSAC Challenge.  Post-editing, a link to this will be placed on chiphack.org.

Half the workshop delegates completed an online survey geared towards the collection of qualitative feedback that can be used to improve Chip Hack in terms of running future events and the materials that are available.

The survey respondents reported that they understood FPGAs better after the event.   Half found the introduction to, and tutorials on, FPGAs and Verilog aided their understanding and the remainder benefited from being able to fine tune their prior knowledge and skills.  The face to face contact with people was noted as beneficial, particularly for people who were self-taught.  Reported difficulties experienced by some people will serve as guidance to make future chip hack events better, particularly for future delegates with little or no experience of FPGAs, Verilog and programming.  Respondents also identified gaps in the materials that are available on chiphack.org that will enhance people’s ability to run their own chip hack events.  Workshop participants report that they are likely to use the materials to run their own chip hack events and
improve their own understanding and knowledge.

Delegates appreciated hearing the history of EDSAC and anecdotes from people with first-hand knowledge and experience who knew key people from the era.

Feedback on the operational side of the event was not formally collected.  Verbally, delegates indicated their satisfaction with the conference facilities provided by Hebden  Bridge Town Hall and Embecosm’s production of the event, but it was noted that workshop delegates will need greater table space at future events.


ChipHack EDSAC Challenge – Hebden Bridge 6/9/2017

ChipHack

ChipHack EDSAC Challenge is a workshop spanning two-and-a-half days to introduce a new generation to silicon chip design and the historic EDSAC computer.

This workshop is suited to complete beginners, as well as people who are experienced chip designers.

With modern low cost FPGA boards silicon chip design is accessible to the individual engineer, whether professional, hobbyist or student.

This workshop starts from the basics (a chip design to flash an LED), works through more complex functionality (UART transmitter and receiver) and concludes by bringing up a complete processor.

The workshop will be built around a reimagining of EDSAC (designed by BCS founding President, Prof. Sir Maurice Wilkes) using modern technology. The workshop will use the MyStorm FPGA board, a modern low-cost board for educational use. (more…)


Open Source SG July Meeting – London 27/7/2017

The BCS OSSG is hosting its next event on 27th July 201718:00 – 21:00 at BCS London1st Floor, The Davidson Building5 Southampton StreetLondonWC2E 7HA, [map] (51.510812-0.121733)

This event is free to attend for both BCS Members and non-members but booking is required. Places are limited; please book as soon as possible.

The event will include talks on trust and provenance in Open Data at GDS, adding security to compilers (LADA project and SECURE project), extending a RISC ISA to add capability enhancements for improved security (CHERI project).

Further details will be added in the next few days.


pkgsrc Conference 2017 – London 1/7/2017

pkgsrc Conference 2017

On the 1st July 2017, 10:00 – 18:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812, -0.121733)

The BCS Open Source SG is this year hosting pkgsrcCon, the annual technical conference for pkgsrc and people working on building and packaging open source software in general. pkgsrc is a framework for building over 18,000 open source software packages consistently across a variety of operating systems running on different CPU architectures.

Read more about the conference here.

This meeting is open BCS and non-BCS members, but registration is required.

Closing date for bookings is Thursday 29 June 2017 at 11:59 pm. No more bookings will be taken after this date.

Update (10th July): the videos & slides and the final report are now available


Getting started with NetBSD on embedded platforms (Part 2) – London 18/5/2017

On the 18 May 2017, 18:00 – 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812, -0.121733)

Please register to attend and share on Lanyrd.

Workshop scope

Following on from the previous workshop, we will be continuing with the theme of NetBSD on embedded platforms. This time covering GPIO access with lua and rapid development with Rump kernel, which we did not get to in the previous workshop due to the lack of time.

If you did not get to attend the previous workshop, not to worry, notes are available and assistance will be provided on the day.

Participant requirements

You will need to bring:

  • Your own laptop (running Windows, Linux or Mac OS X);
  • A Raspberry Pi or BeagleBone Black;
  • An appropriate SD card for your board;
  • USB card reader to write a new OS image onto said SD card;
  • An ethernet cable to connect board to laptop and/or a USB UART/FTDI adapter to access the board via the serial console.

Windows 10 users

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Getting started with NetBSD on embedded platforms – London 20/4/2017

NetBSDOn the 20 April 2017, 17:30 – 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812, -0.121733)

Please register to attend and share on Lanyrd.

Workshop scope

You’re hired at the latest startup as a hardware engineer and required to build the firmware which will run on “The Greatest Next Generation Appliance” (GNA). The GNA boots, prints a message and interacts with a device (in this case an LED).

In this workshop we cover how a person with an interest and a focus on hardware can make progress with the software side by using the NetBSD operating system and the features it offers to save considerable time and effort.

  • NetBSD supports a wide & diverse range of systems & CPU architectures.
  • Support for cross compilation is offered by default and works out of the box.
  • There is a high level language interface to interact with the system internals.
  • File integrity verification support to detect tampering of binaries and preventing execution is builtin.
  • An instance of the kernel can be run as a user process on different operating systems where rapid development can take place.

Things we will cover:

  1. An introduction to cross-compilation with build.sh and constructing an image to boot on your hardware.
  2. Interacting with the system using Lua (which is embedded in the kernel, avoiding having to write C or have knowledge of OS internals) to e.g. access GPIO.
  3. Preventing the execution of tampered or unauthorised binaries with veriexec.
  4. Using rump kernel for rapid development away from a potentially slow dev board.

(more…)