London Open Source Meetup for RISC-V

October 18, 2021 @ 6:00 pm – 8:30 pm
BCS London
25 Copthall Ave
London EC2R 7BP

Our quarterly meetup for the London open source community, focusing on RISC-V and open source, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group.  These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking. This month we have a strong AI theme.

This will be a hybrid meeting, with some people attending in person in London and others able to join via videoconference.  You are invited to join and socialize from 18:00, talks will run from 18:30-20:00 with 30 minutes at the end for further discussion and socializing.  Due to COVID-19 restrictions, for those wishing to attend in person, registration is essential.  We anticipate numbers attending will still be restricted.

Register here to attend in person

For remote attendees, there is no requirement to register, you can just connect to the videoconference using BigBlueButton using this link.  Thank you to GWDG for providing hosting for this meeting.  We are also recording the talks for later posting on our YouTube channel.

The livestream link will be open from 18:00 for networking, and the event will start at 18:30 prompt. We’ll keep the link open afterwards for discussion.

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The videos of the meeting are online here.

Q&A with Olof Kindgren, creator of SERV

Olof Kindgren, FOSSi Foundation

The award-winning SERV is the world’s smallest RISC-V CPU. It’s the perfect companion whenever you need a bit of computation and silicon real estate is at a premium. This presentation offers an introduction to SERV, what makes it so small and where it is and can be used. It will also take a closer look at what has happened with SERV the last year, what’s in store for the future and a couple of project ideas if YOU are looking for a a fun project.

Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.

Accelerating Neural Networks using RISC-V and Open Standard Software

Charles Macfarlane, CBO, Codeplay Software

Neural Networks are foundational AI constructs for recognizing relationships in data requiring processing massive datasets in the form of tensors. Tensor processing is central to AI and machine learning applications. Algorithms such as convolutions and pooling involve running operations on matrix and vector data structures. It is these operations that can be executed efficiently on processors that are designed to allow many common operations to run in parallel across many cores, this has become a common use case for GPUs in recent years. But companies are also looking at ways to develop more specialised processors to tackle the performance challenges of modern AI applications. This presentation will explain how our team accelerated the execution of a tensor-based neural network on the RISC-V Spike simulator using open source and open standard software. We will explore how our demo application was built using the open source Eigen, SYCL-BLAS and SYCL-DNN libraries with the ResNet50 neural network commonly used for processor benchmarks.

There will be an emphasis on the open source software we use and develop to enable our software stack.

Charles is Chief Business Officer and has been with Codeplay since 2014. Charles graduated from Glasgow University with an honours degree in Electronic Systems and Microprocessor Engineering. Charles then followed a career doing ASIC chip design in GEC Plessey Semiconductors and Pioneer, applications engineering and marketing with VLSI/Philips/NXP in South France, and product marketing director with Broadcom® in Cambridge for mobile multimedia solutions used by Nokia®, Samsung® and Raspberry Pi®.

A simple extension to CV32E40P to accelerate AI inference

Veronia Iskandar, TU Dresden
William Jones, Head of AI and Machine Learning, Embecosm

We present the development of a simple ISA extension to the Open Hardware Group’s CV32E40P core, extending earlier work from the University of Southampton (see the presentation to the London RISC-V meetup earlier this year). We are creating a physical realization on the Nexys-A7 FPGA board, with much of the work completed under the 2021 Google Summer of Code program. We add a subset of just 8 instructions from the V extension to the Open Hardware Group CV32E0P core. The CV32E40P features an Auxiliary Processing Unit (APU) interface. This follows a subset of the OBI interface used to communicate with system memory. We use this interface for the accelerator. Several modifications were required to the core RTL in order to better support the architecture of the accelerator, primarily in regards to multi-cycle instructions. The accelerator and core RTL are then taken through the stages of FPGA development, starting from bitstream generation to debugging binary files on the FPGA. The result is a small RV32 core which speeds up the standard TinyMLPerf benchmark more than 5-fold. An important result for those looking to accelerate low energy AI inference at the edge and a free and open reference code base for others wishing to build on this work.  In this talk we will give a status update on the project.

Veronia Iskandar is a PhD candidate in Computer Science in the Adaptive Dynamic Systems (ADS) chair at the Technical University in Dresden, Germany, since March 2020. Before joining the ADS research group, she studied Computer and Systems Engineering at Ain Shams University in Egypt where she received her Bachelor degree in 2013 and her Master degree in 2018. Her current research interests include hardware/software co-design, architectures for 3D chips, and efficient memory systems.

William Jones has a research background in computational neuroscience, with a focus on artificial neural networks and machine learning techniques. He leads Embecosm’s AI team, working on applying these machine learning and AI techniques to Embecosm’s domains of interest. Dr Jones completed his PhD at the University of Kent on the subject of computational models of perception.