The BCS OSSG and the OSHUG are hosting 3 talks on Open Source Chip Designs.
The event will be held on Thursday 18th June at BCS HQ – 5 Southampton Street, London, WC2E 7HA from 6:00pm to 8:00pm.
This event is free to attend for both BCS Members and non-members but booking is required.
Note: Please aim to arrive by 6:15 as the event will start at 6:30 prompt.
BERI: An open RISC softcore for research and experimentation
BERI (the Bluespec Extensible RISC Implementation) is a softcore processor jointly developed by SRI International and The University of Cambridge. It implements a superset of the MIPS III ISA in Bluespec, a high-level HDL and supports a fully Open Source, permissively licensed, software stack comprising the FreeBSD operating system and the LLVM compiler suite. This talk will describe the design of the BERI processor and its use.
BERI was created to facilitate experimentation at the boundaries between CPU architecture, operating systems, and programming languages. It runs in Altera and Xilinx FPGAs, including the NetFPGA 10G board. At 100MHz, it is fast enough to use as a real computer (albeit a fairly slow one).