We continue our quarterly meetup for the London open source community, focusing on RISC-V, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group. These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking.
Once again, due to COVID-19 it will be a purely virtual meetup. We’ll be live streaming using BigBlueButton to provide a rich online experience for participants. As always the talks will be recorded for later upload to YouTube. You are invited to join and socialize from 18:00, talks will run from 18:30-20:30 with 30 minutes at the end for further discussion and socializing.
In a change to our past practice, there is no requirement to register, you can just connect to BigBlueButton on this link.
The videos of the event are now available on YouTube.
Developing and testing TensorFlow Lite Micro edge AI algorithms on RISC-V and FPGAs
Michael Gielda, Antmicro
With the increasing demand for small and energy-efficient devices with AI capabilities, new tools and workflows are needed to develop so-called TinyML applications. In a project with Google’s TensorFlow Lite MCU team, Antmicro has been helping improve the CI infrastructure for one of the world’s most famous ML frameworks. TF Lite Micro users can now run their machine learning framework on virtual hardware for demonstration, CI and testing. Renode allows ML developers to repeatedly and reliably test various demos, models and scenarios on a variety of hardware, including a wide range of RISC-V platforms, both soft and ASIC implementation, e.g. the recently added Core-V MCU, while its co-simulation capability enables co-development with physical FPGAs, which can be used to build AI/ML accelerators. In collaboration with QuickLogic, Antmicro has also been enabling source FPGA tooling for the eFPGA found in the Core-V MCU, enabling users to kick-start flexible prototyping and pre-silicon development of ML-capable systems based on RISC-V + FPGA. Join the talk to learn more about the advantages of using Renode’s simulation, testing and CI capabilities for the development of machine learning applications.
Michael Gielda is VP Business Development and co-founder of Antmicro. With a background in both computer science and the humanities, he is an ardent believer in using open source to advance entire industries. Michael is vice-chair of Marketing in the RISC-V Foundation and Chair of Marketing and Outreach in CHIPS Alliance.
Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning
Pete Alexander, John Holden, Harry Cooper, Byron Theobald, Aaryaman Bhattacharya, Matthew Johns, University of Southampton
The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to add custom instruction extensions to the processor targeting specific applications. This project has taken an existing core and designed an accelerator to handle vector instructions to speed up the inference of neural networks. As a benchmark, tinyMLperf has been used which has required vector instructions to be integrated into Tensorflow Lite for Microcontrollers. The goal is to show the benefits of custom instructions and stimulate similar work in the community.
This project has been completed by six fourth-year Electrical and Electronic Engineering students from the University of Southampton. This group project is required for the MEng degree and ran over 10 weeks in Autumn 2020. Each member of the team has different backgrounds, from digital design, to AI expertise, to compiler experience. The project has been supported by Embecosm.
Developing Diosix: An open-source RISC-V bare-metal hypervisor from scratch in Rust
Chris Williams, diodesign
Diosix bridges two interesting and emerging worlds of technology: Rust and RISC-V. As a bare-metal, type-1 hypervisor, Diosix strives to bring the security, reliability, and speed of Rust to the lowest levels of RISC-V systems. The result is the ability to run multiple guest operating systems, each secured within their own hardware-enforced virtualized environments, on a single RISC-V host.
This allows developers to build and test iterations of system and application software without having to reflash and reboot their in-development hardware, as well as run a mixture of isolated guests.
This presentation will walk through the architecture of Diosix, how it uses base RISC-V features to provide hardware-enforced virtualization, its progress in running guest operating systems such as Linux, and the project’s next steps. Source code and documentation can be found here.
Chris is a San Francisco-based technology journalist at The Register, a publication that covers enterprise IT, information security, and software development. He has worked in the media for the past 15 years as a writer and editor, and his background is in electronic engineering. To keep up with changes in the industry, Chris writes and shares open-source software in his spare time.