Our quarterly meetup for the London open source community, focusing on RISC-V and open source, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group. These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking. The theme for this quarter’s meeting is optimizing code size for RISC-V.
Due to COVID-19 this will again be a purely virtual meetup. We’ll be live streaming using BigBlueButton to provide a rich online experience for participants. As always the talks will be recorded for later upload to YouTube. You are invited to join and socialize from 18:00, talks will run from 18:30-20:00 with 30 minutes at the end for further discussion and socializing.
There is no requirement to register, you can just connect to livestream using BigBlueButton on this link. We are also recording the talks for later posting on our YouTube channel.
The livestream link will be open from 18:00 for networking, and the event will start at 18:30 prompt. We’ll keep the link open afterwards for discussion.
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Evaluating the proposed Zce extension
Ibrahim Abu Kharmeh, Huawei Bristol, UK
RISC-V is an open source fast growing ISA designed at the University of California, Berkeley. The ISA was designed to target various wide range of applications starting from HPC to Embedded Systems. For RISC-V to be competitive in embedded space, its code size density has to be at least on par or better than commercial alternatives.
While RISC-V contains several features like variable instruction length and compressed instruction that should help achieving that. Several benchmarks  indicate that RISC-V code density is worse than that of these alternatives. Luckily, RISC-V was designed to accommodate for extensions to enhance various aspects of its performance.
One of those extensions is Zce, this extension purpose is to help close the gap of code density with these alternatives. In this presentation, I will present the evaluation criteria used for comparison, review the main contributing factors to the worse code density performance, review the main Zce instructions for better code density (PushPop, TBLJAL and Multimove), and present their approximate savings.
 Perotti, Matteo, et al. “HW/SW approaches for RISC-V code size reduction.” Workshop on Computer Architecture Research with RISC-V (CARRV 2020)
Ibrahim has recently completed an Electronic Engineering MSc (Micro Electronics Stream) at the University of Southampton. During his masters degree, he researched the feasibility of implementing a NISC based processor for signal processing. He is currently working for Huawei Bristol where he is researching, modelling and benchmarking code size optimization for the RISC-V extension Zce. Previously, he worked as an embedded HW/SW design engineer for just over 2 years.
The LLVM inliner and MI: Mutual Inlining
Nidal Faour, Western Digital Corporation, Israel
I will be presenting the work done by Western Digital on the LLVM inliner and the solutions we are exploring to improve it.
Nidal Faour is a toolchain Engineer at Western Digital CTO group. Nidal started at Western Digital 10 years ago. After 5 years of experience in Embedded systems as a FW engineer, then over 4 years of experience in build systems he joined the CTO team, where he started working on the RISC-V toolchain and doing research on RISC-V code size and footprint for embedded systems.
The RISC-V Online Tutor
Fearghal Morgan, NUI Galway, Ireland
RISC-V Online Tutor provides structured, self-paced RISC-V architecture and applications training and reference. It uses the vicilogic platform (online learning, remote FPGA prototyping and course builder). The course browser transparently interacts with remote RISC-V FPGA hardware. Lessons control remote hardware input signals, probe internal RISC-V signals, and overlay signal state as widgets on interactive course diagrams. The strategy provides a visually-rich, interactive learn-by-doing experience.
Users learn RISC-V assembly, architecture design, RISC-V code HDL capture, pipelining and hazards, and introductory-level C to assembly. The platform can be used to extend training modules to support RISC-V training, e.g, on RISC-V extension hardware implementation.
The presentation describes the course structure, pedagogy examples, course build process, recent user experience, and analytics.
Fearghal Morgan is a lecturer/researcher in the National University of Ireland, Galway (NUI Galway), working in online learning and remote labs, reconfigurable computing and bio-inspired systems. Fearghal has worked in industry (ASIC and Comms design), along with 28 years in University teaching and research. Publications: Google Scholar