Our quarterly meetup for the London open source community, focusing on RISC-V and open source, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group. These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking.
Due to COVID-19 this will again be a purely virtual meetup. We’ll be live streaming using BigBlueButton to provide a rich online experience for participants. As always the talks will be recorded for later upload to YouTube. You are invited to join and socialize from 18:00, talks will run from 18:30-20:00 with 30 minutes at the end for further discussion and socializing.
There is no requirement to register, you can just connect to the livestream using BigBlueButton using this link. Thank you to GWDG for providing hosting for this meeting. We are also recording the talks for later posting on our YouTube channel.
The livestream link will be open from 18:00 for networking, and the event will start at 18:30 prompt. We’ll keep the link open afterwards for discussion.
CFU Playground: Model-specific Acceleration on FPGAs
Tim Callahan, Google
This talk describes the CFU Playground, an open-source framework that an engineer, intern, or student can use to design and evaluate enhancements to an FPGA-based soft RISC-V processor, specifically to increase the performance of machine learning (ML) tasks through the addition of custom function units (CFUs). The goal is to abstract away most infrastructure details so that the user can get up to speed quickly and focus solely on adding new processor functions, exploiting them in the computation, and measuring the results.
The presentation describes the process of identifying hot spots in the code during an inference using a specific model, constructing a CFU to support new custom instructions, modifying the TensorFlow Lite kernel library to use these new instructions, measuring the results, and iterating. The goal is not to design a general ML accelerator; the goal is to jointly specialize the processor and ML kernels just for the model of interest.
All IP and software used is open sourced and licensed permissively — the open RISC-V ISA that allows new custom instructions, the VexRiscv soft core implementation, the LiteX system-on-chip IP, the Symbiflow FPGA toolchain, Renode and Verilator simulators, and TensorFlow Lite kernel libraries. Thus, the combined CPU, CFU, and kernel libraries that the user develops are not tied to any particular FPGA vendor; there are no licensing restrictions or fees; and there is no dependence on any black box proprietary tools.
Tim Callahan works at Google with the open source FPGA toolchain (Symbiflow) team. His work is to help make FPGA development more accessible, fun, and rewarding.More generally, he enjoys anything that involves optimizing the hardware/software boundary, He has degrees from UC Berkeley, Cambridge University, and the University of Minnesota.
Pineapple One: an open-source discrete 32-bit RISC-V CPU
This talk will be about a 32-bit homemade RISC-V CPU, made only out of discrete logic components and memories. There are no FPGAs nor any microcontrollers used and the whole project can be found on GitHub as open-source. The goal of this project is to introduce more people to RISC-V with a CPU that can be build by anybody who can solder. The presentation will be supplemented by a live demo of the CPU as well as some plans for the upcoming version.
Filip Szkandera is a student of Higher School and Secondary School of Electrotechnical Engineering in Olomouc, Czech Republic. He is interested in electronics, especially in building his own CPU(s). He is 19 years old.
Q&A with Olof Kindgren, creator of SERV
Olof Kindgren, FOSSi Foundation
The award-winning SERV is the world’s smallest RISC-V CPU. But how does it work, what makes it so small and what is it good for? This is your chance to participate in a fully immersive multimedia edutainment experience to learn all the answers.
Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.