We are resuming our quarterly meetup for the London open source community, focusing on RISC-V, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group. These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking.
This time it will be a virtual meetup, and we’ll be livestreaming using BigBlueButton to provide a rich online experience for participants. As always the talks will be recorded for later upload to YouTube. When you register you’ll also get a link to a GoToWebinar session, which we will use as fallback if there is a problem with BigBlueButton, since we are still learning the technology.
Please register using the link above. For any with connection issues, we’ll also tweet the link on @BCSOSSG just before the meeting starts.
Porting Rust to 64-bit RISC-V GNU+Linux
This year several GNU+Linux distributions have released stable 64-bit RISC-V ports; which lead users and package maintainers to expect access to the Rust toolchain on RISC-V. I spent some time getting Rust’s 64-bit RISC-V target to the point that the project felt comfortable publishing official RISC-V builds. This talk explains how to port Rust to a new target and talks through some bugs fixed along the way.
Tom is interested in free software, cryptography and embedded systems. In 2017 he published a paper through MDPI. The paper suggests and evaluates the performance of a privacy preserving smart metering protocol. In 2018 Tom graduated with a masters degree in electronic engineering from the University of Southampton and started work as a software engineer at Codethink. At Codethink Tom helps clients align their embedded GNU+Linux systems more closely with upstream free software projects. Recently, Codethink sponsored Tom to improve support for RISC-V in the Rust ecosystem.
A Plan 9 C Compiler for RV32GC and RV64GC
The Plan 9 C compiler originated at Bell Labs alongside the Plan 9 and Inferno operating systems. It was part of the initial development toolchain for Go (before that language became self-compiling), and is a useful stand alone tool for building embedded software. A new RISC-V version of the Plan 9 C compiler, assembler and linker, targeting RV32IM cores such as PicoRV32, was announced by the author at ORCONF in 2018. The toolchain has now been expanded with floating point, compressed, and 64-bit instruction capability.
Richard Miller is a consulting engineer working in the borderland between software and hardware, on operating systems, programming language implementation, and digital logic design. His first C programming project was in 1977, adapting Dennis Ritchie’s original 16-bit PDP-11 C compiler to generate code for the 32-bit Interdata 7/32.
Porting the GNU CORE-V Toolchain
Pietra F T Madio, @7pietraferreira
Over recent years, RISC-V has taken off in both academia and industry. One RISC-V variant, CORE-V, developed by the Open Hardware Group, adds extensions which can improve performance and reduce code size. As part of this effort, the Open Hardware group have decided to build a robust set of GNU tools targeting CORE-V.
In the first part of this presentation, we will discuss adding support for hardware loop instructions to GNU binutils. This has involved making changes to the GNU assembler, gas, and the GNU linker, ld. We will explain in technical detail how we ported this custom extension to binutils as well how we tested the resulting CORE-V assembler and linker.
The second part of this presnetation will focus on adding hardware loops to GCC in three places; as built-in (intrinsic) funcions, as code-generation patterns for the compiler and within target specific optimization. We shall give special attention to memcpy, the function to copy blocks of memory, and which GCC uses every time a struct is assigned or returned as a result.
To encourage engagement with this project we have provided pre-built binaries, source code, scripts and test results for the comunity. Additionally, patches are welcome as pull requests against the Open Hardware Group repositories for corev-binutils-gdb and corev-gcc on GitHub.
Mary Bennett is a tool chain engineer at Embecosm, developers of open source compilers, operating systems, models and AI. She graduated from the University of Surrey with a degree in EEE and a love of Jui Jitsu and climbing. Mary is best know for her work as Chair of the RISC-V Academia and Training group from 2018 to early 2020. She was winner of the UK Electronic Skills Foundation Scholar of the Year 2019. Mary is a key engineer in the RISC-V CGEN project and CORE-V Binutils-GDB and GCC projects, and can be found on YouTube speaking on these subjects at numerous conferences over the past three years.
Pietra F. T. Madio moved to the UK from Brazil and has been working as a software engineer for Embecosm since November 2018. Pietra was previously undertaking research and implementation of neural networks using Keras and TensorFlow. She has also written a series of blog posts on implementing face recognition on the Google Coral development board. She currently is a key engineer at the CORE-V Binutils-GDB and GCC project, being the project manager for Binutils-GDB. Pietra previously presented at the BCS as part of the 2019 Women in Open Source meeting and also spoke at the OSD Forum 2020 about her work on the Core-V Binutils-GDB project.
Jessica Mills is a Software Tool Chain Engineer at Embecosm, developers of open source compilers, operating systems, models and AI. She graduated from the University of Leeds with a masters degree in Electronics and Computer Engineering. Jessica is a key engineer in both the CORE-V Binutils-GDB and GCC projects, being the project manager for GCC. She has previously presented this work at the OSD Forum 2020.