FPGA projects past, planned and possible – London 16/2/2017

On the 16 February 2017, 18:00 – 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA,[map] (51.510812, -0.121733)

Please register to attend and share on Lanyrd.

The fifty-fifth meeting will feature a series of shorter talks that explore past, planned and possible projects which use FPGAs.

FPGA Projects – What would I build and why would I want to

PLAs have been interesting ever since the 70s when digital logic often became complex, consuming unnecessary space and power. Back then the cost of PLA deployment was high and it has continued to be high until recently. Now that we have powerful, low cost development platforms and relatively cheap FPGAs the cost equation has shifted radically.

Paul Tanner is a consultant, developer and maker in wood, metal, plastic, electronics and software. His day job is IT-based business improvement for SMEs. By night he turns energy nut, creating tools to optimise energy use. Paul graduated in electronics and was responsible for hardware and software product development and customer services in several product and service start-ups, switching to consulting in 2000.

Using FPGAs to solve realtime problems

Microcontrollers a great platform to solve basic control problems in electronics, with simple motor drivers and sensors readily avaiable and easy to integrate. However, when the motor control becomes more complex with BLDC and FOC things get much more tricky. When you have to use multiple BLDC motors and more complex sensors with image processing the poor microcontroller quickly becomes to swamped to provide control in realtime. This is where adding FPGA technology makes a great deal of sense particularly in mutli-discipline projects like robotics where many sensors, motors and image processing will need to be managed and controlled concurrently. A robotics platform must therefore contain both concurrent hardware resources, algorithmic control through soft or hard cores along with communication protocols.

Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning, inference and image processing for embedded applications using FPGA and multi-cores. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace and myStorm FPGA development boards.

FPGAs in the Cloud?

It is no secret that FPGA based computing machines are great at dealing with certain types of workloads that conventional CPU based machines can not efficiently handle. These machines, alongside their GPU and even custom ASIC based brethren, have been filling up racks in large data centres all over the globe helping speed up systems that have components of machine learning, complex analytics and even video processing.

This short talk will have a look at the state of FPGAs in the datacenter and discuss the recent developments around the availability of FPGA equipped computing nodes in commodity cloud providers.

Omer Kilic is an Embedded Systems Engineer who enjoys working with small connected computers of all shapes and sizes. He works at the various intersections of hardware and software engineering practices, product development and manufacturing.

Chip Hack 2017 & EDSAC Challenge

This talk will introduce and issue a call for participation for two events that are being hosted as part of the Wuthering Bytes technology festival, that will take place in Hebden Bridge in September, in the week following Open Source Hardware Camp 2017.

Chip Hack is a two day hands-on workshop that provides a gentle introduction to programming FPGAs and is aimed at novices with no prior experience of Hardware Description Languages (HDLs) or FPGAs. This will be followed immediately by a challenge event, during which a small team of experts will work to extend a basic functional FPGA model of EDSAC — the pioneering computer designed and constructed at Cambridge University, and which was operational by 1949.

Dr Jeremy Bennett is founder and Chief Executive of Embecosm, a consultancy implementing open source compilers and chip simulators for major corporations around the world. He is a author of the standard textbook “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003). Contact him at: jeremy.bennett@embecosm.com.

7th February update: 2 extra talks!

Deploying your FPGA toolchain consistently regardless of your development environment

With an open source tool chain for an open hardware fpga, we’re free to work in the environment of our choice. What may differ between platforms is how we put the components together, from requiring software dependences to administrative commands needed to be executed in order to build to software successfully.

pkgsrc is a cross platform packaging system which allows you to deploy open source software consistently, regardless of the environment it is operating on. This means should you desire to install the icestorm tool chain, the steps required to build or install packages is the same whether you’re running a flavour of Linux, Mac OS or Windows.

This lightning talk will introduce pkgsrc and how you can get started quickly with icestorm and other tools to help with your hardware project.

Sevan Janiyan is founder of Venture 37, which provides system administration & consultancy services. As a fan of operating systems and computers with different CPU architectures, in his spare time he maintains builds of open source software on a variety of systems featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube & OMRON LUNA-88K2 one day.

Multicore Made Simple – Conducting a Chorus of Cores on an FPGA

FPGA technology makes it simple to build a multicore CPU, by instantiating multiple copies of a soft processor design on a single chip. The challenge is to connect and coordinate the cores into a resource which is useful for application programming. While traditional multicore processors include shared memory, shared buses and/or general communications networks, all of these are costly in hardware resources and complexity, and subtle details of synchronization and cache coherency can make programming difficult and risky. Building our own system on an FPGA, we can choose a minimalist “shared nothing”
architecture, with only local memories and simple synchronous point to point communications links in a topology tailored to the application. As an example of this approach, I’ll demonstrate a 40 voice (plus
conductor) polyphonic digital audio synthesizer, running on an array of
41 Nios2 cores on an Altera Cyclone II.

Dr Richard Miller has had a long career in the borderlands between hardware and software, in academia and industry and now as an independent consultant. Particular interests have been operating systems portability (starting in 1977 with the world’s first UNIX port, from
PDP/11 to Interdata 7/32 at the University of Wollongong; and most recently porting the Plan 9 OS to the Raspberry Pi); programming language implementations in constrained environments (e.g. a LOGO interpreter on a 48KB Apple II; and a JavaCard JVM and runtime library on a smartcard with a 8KB of RAM and 1MB of flash); parallel computing infrastructure (on hardware ranging from Transputers to the Cray T3D); and embedded systems firmware (e.g. a complete Bluetooth stack for a range of prototype phones and tablets). Current work in progress includes building a communications network on an FPGA, for a microcluster of Raspberry Pi Zeroes.

Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt.

Getting started with FPGAs and Verilog using project IceStorm and myStorm – London 1/12/2016

The BCS OSSG and the OSHUG are hosting a talk on educating the next generation.

The event will be held on Thursday 1st December at Prince Philip Room, The Royal Society of Arts, 8 John Adam Street, London, WC2N 6EZ, [map] (51.5093963-0.1227355) from 9:00 to 17:00.

Please register to attend and share on Lanyrd.

A further meeting on Educating the next generation will then follow in the evening, but at a different venue.

Please note that if you intend to attend both the workshop and evening meeting, you must register separately for each of these!

Workshop details

In this workshop we will build some basic Verilog blocks and modules targeting low power, low cost FPGAs from the Lattice iCE40 series. The workshop will operate using a complete open source Verilog toolchain based around Yosys and Arachne-PNR, which can be run on Linux and OS X. We will cover basic sequential and combinational logic blocks. In addition we will show you how you can combine simple ARM microcontroller code running alongside and communicating with Verilog peripherals synthesised on a Lattice iCE40 FPGA, all running together on myStorm.

This workshop will give participants a real taste of FPGA development in an open source software environment, using open source hardware.

Ken Boak started his professional career at BBC Research Department in 1986 working on digital signal processing systems for HDTV and subsequently over 30 years, a mix of 10 other technology companies, both UK and US based, in the fields of instrumentation, automation, telemetry telecomms.

Ken has been interested in energy monitoring since the early 1990s, when he constructed a 4 seater electric car, and provided rudimentary energy analysis of the battery charge and discharge cycles. In 1998 he joined a South London company and designed a low power wireless, monitor device for automatic, remote gas and electricity meter reading.

In 2009 Ken worked on the Onzo Energy Monitoring Kit, a commercial device that was ultimately distributed to Southern Electric customers. Then in 2010 he produced a series of educational devices to teach engineering undergraduates the principles of photovoltaic energy systems.

Ken has continued his interests in energy monitoring, working collaboratively with Megni on the OpenEnergyMonitor project, the open Inverter Project and also for All Power Labs in Berkeley, California, where he was involved in power monitoring of wood gasifier generator sets. He tries to live a low impact lifestyle in a modest Edwardian house in Surrey, with a little help from modern electronics.

Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning for embedded applications using Motes on FPGA and emerging Asics. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace.

What to bring

Participants must bring a laptop computer and ideally one that is running either Linux or OS X. If your laptop is running Windows, you should also bring along a Raspberry Pi or similar Linux SBC, that you can use to build the toolchain and program myStorm over USB.

Note: Please aim to arrive by 08:45 as the workshop will start at 09:00 prompt.

Educating the Next Generation (myStorm update, micro:bit, encouraging next generation) – London 1/12/2016

The BCS OSSG and the OSHUG are hosting a talk on educating the next generation.

The event will be held on Thursday 1st December at CSC, 3rd Floor, The Wallbrook Building, 25 Wallbrook, London, EC4N 8AQ,  [map] (51.5103063-0.0961973) from 6:00pm to 8:00pm.

Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt.

This event is free to attend for both BCS Members and non-members but booking is required. Places are limited; please book as soon as possible.

myStorm update

myStormmyStorm is an open hardware and software FPGA development platform that is based around a Lattice iCE40 FPGA, which uses the fully open source IceStorm/Yosys/Arache-pnr toolchain for development. It is low cost and aims to provide a gentle on-ramp for those who are new to RTL development and working with FPGAs. In this talk we will hear a report from the workshop which took place earlier in the day, together with a status update on the myStorm project.


The future of Open Source: silicon chip design for the masses, musical instruments and algorithms as pictures – London 20/10/2016

This year’s BCS OSSG AGM will be held on Thursday 20th October at the BCS HQ, First Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA from 6:00pm to 8:45pm.

The AGM will be followed by four talks from our student prize winners and from the designers of MyStorm, an ultra-low cost FPGA board.

This event is free to attend for both BCS Members and non-members but?booking is required. Places are limited; please book as soon as possible.

Note: Please aim to arrive by 18:00 as the event will start at 18:15 prompt.

The timetable for the evening will be:

18:00 – Registration & refreshments
18:15 – BCS AGM and election of officers
18.45 – The Light Theremin Project
19:00 – The Next Generation of Open Source Engineers
19:15 – The use of Open Source projects to scaffold the development of new programmers
19:30 – The MyStorm project
20:00 – Sandwiches + networking
20:45 – Close


Chips Pt.3 (BERI, Do we need separate Hardware Construction languages? OpenTransputer) – London 18/06/2015

The BCS OSSG and the OSHUG are hosting 3 talks on Open Source Chip Designs.

The event will be held on Thursday 18th June at BCS HQ – 5 Southampton Street, London, WC2E 7HA from 6:00pm to 8:00pm.

This event is free to attend for both BCS Members and non-members but booking is required.

Note: Please aim to arrive by 6:15 as the event will start at 6:30 prompt.

BERI: An open RISC softcore for research and experimentation

OpentransputerBERI (the Bluespec Extensible RISC Implementation) is a softcore processor jointly developed by SRI International and The University of Cambridge. It implements a superset of the MIPS III ISA in Bluespec, a high-level HDL and supports a fully Open Source, permissively licensed, software stack comprising the FreeBSD operating system and the LLVM compiler suite. This talk will describe the design of the BERI processor and its use.

BERI was created to facilitate experimentation at the boundaries between CPU architecture, operating systems, and programming languages. It runs in Altera and Xilinx FPGAs, including the NetFPGA 10G board. At 100MHz, it is fast enough to use as a real computer (albeit a fairly slow one).