OSSG AGM, Reimagining EDSAC, NetBSD Updates, Semantic and Change Coupling of Software Classes – London 19/10/2017

The BCS OSSG is hosting its next event on 19th October 201718:00 – 21:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA, [map] (51.510812-0.121733)

This event is free to attend for both BCS Members and non-members but booking is required. Places are limited; please book as soon as possible.

The meeting this month will start with the BCS OSSG AGM and this will be followed by a talk on recent and planned improvements to NetBSD, a report from Chip Hack EDSAC Challenge, and finally a talk on the interplay between semantic coupling and co-change of software.

BCS Open Source SG – AGM

All members of OSHUG are welcome to attend and OSHUG members are encouraged to put themselves forward to join the committee. In particular we would welcome anyone to join the event organizers who arrange the speakers for each month and the occasional all-day workshops. Currently we have Sevan Janiyan, @ndy Bennett and Andrew Back as event organizers on the committee.

Updates to the NetBSD operating system since OSHUG #57 & #58

NetBSDSince the workshops held earlier this year, numerous changes have been made to the NetBSD operating system to ensure future workshops are easier for users and work smoother from the outset. This talk will cover some of the improvements made so far and what’s currently in the works. From wrestling with the u-boot firmware to new tools included in the os and much more.

Sevan Janiyan is founder of Venture 37, which provides system administration & consultancy services. As a fan of operating systems and computers with different CPU architectures, in his spare time he maintains builds of open source software on a variety of systems featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube & OMRON LUNA-88K2 one day.

Reimagining EDSAC: The ChipHack experience

ChiphackChipHack is an occasional 2 day workshop introducing students and hobbyists to FPGA design. This year, ChipHack was sponsored by the BCS OSSG and Computer Conservation Society. To celebrate the 60th anniversary of the BCS, the workshop was extended by half a day and attempted to reimagine one of the earliest valve computers, EDSAC, designed by the BCS’ founding president, Prof Sir Maurice Wilkes.

Merry Bennett led the team putting together the technical content of the workshop. She will report back on what was achieved, from the three implementations of the computer, to the diverse reimagining of the original peripherals. The result is a legacy of lectures and videos, to allow anyone to run their own ChipHack course.

The Interplay between Semantic Coupling and Co-Change of software classes

During maintenance, developers must ensure that related entities are updated to be consistent with these changes. Studies in the static change impact analysis domain have identified that a combination of source code and lexical information outperforms using each one when adopted independently. The presentation has two aims: first, to compare the effectiveness of measuring semantic coupling of OO software classes using (i) simple identifier based techniques and (ii) the word corpora of the entire classes in a software system. Second, to empirically investigate the interplay between semantic and change coupling.

Dr Andrea Capiluppi joined the Department of Computer Science at Brunel University London (UK), as a Lecturer in Software Development in May2012. Between 2009 and 2012 he was at University of East London, working as a Senior Lecturer in Software Engineering. Before that, he worked as a Senior Lecturer and at University of Lincoln between 2006 and 2009. Andrea’s research and teaching interests focus on Software Evolution and Maintenance, as well as the construction, evaluation and maintenance of Social Networks. Andrea is mostly interested in the use of open technologies and in understanding how they can improve learning and teaching as well as the production of software and other artefacts.

After-event follow up

Update from Judith Jones (Embecosm) on behalf of the organisers: Following our recent successful Chip Hack EDSAC Challenge, sponsored by
the BCS, I am pleased to provide you with feedback, as follows:

Of 80 registrations for the Chip Hack EDSAC 2017 event, 67 people attended.  The event was designed to be a collaborative learning experience and brought together 3 expert silicon chip designers, 11 experienced people, 17 people with some experience and 36 complete beginners.  The legacy of the event is a body of materials available under open source licence to enable people to run their own Chip Hack EDSAC events in the future, thereby making silicon chip design accessible to the individual engineer, whether professional, hobbyist or student.  The technical materials are freely available through, myStorm boards will be freely loaned through the BCS (stored at, and managed by, Embecosm) and recordings of the workshops and talks will be available, post-editing, through  In addition, Andrew Back is producing a documentary with the working title Chip Hack EDSAC Challenge.  Post-editing, a link to this will be placed on

Half the workshop delegates completed an online survey geared towards the collection of qualitative feedback that can be used to improve Chip Hack in terms of running future events and the materials that are available.

The survey respondents reported that they understood FPGAs better after the event.   Half found the introduction to, and tutorials on, FPGAs and Verilog aided their understanding and the remainder benefited from being able to fine tune their prior knowledge and skills.  The face to face contact with people was noted as beneficial, particularly for people who were self-taught.  Reported difficulties experienced by some people will serve as guidance to make future chip hack events better, particularly for future delegates with little or no experience of FPGAs, Verilog and programming.  Respondents also identified gaps in the materials that are available on that will enhance people’s ability to run their own chip hack events.  Workshop participants report that they are likely to use the materials to run their own chip hack events and
improve their own understanding and knowledge.

Delegates appreciated hearing the history of EDSAC and anecdotes from people with first-hand knowledge and experience who knew key people from the era.

Feedback on the operational side of the event was not formally collected.  Verbally, delegates indicated their satisfaction with the conference facilities provided by Hebden  Bridge Town Hall and Embecosm’s production of the event, but it was noted that workshop delegates will need greater table space at future events.

ChipHack EDSAC Challenge – Hebden Bridge 6/9/2017


ChipHack EDSAC Challenge is a workshop spanning two-and-a-half days to introduce a new generation to silicon chip design and the historic EDSAC computer.

This workshop is suited to complete beginners, as well as people who are experienced chip designers.

With modern low cost FPGA boards silicon chip design is accessible to the individual engineer, whether professional, hobbyist or student.

This workshop starts from the basics (a chip design to flash an LED), works through more complex functionality (UART transmitter and receiver) and concludes by bringing up a complete processor.

The workshop will be built around a reimagining of EDSAC (designed by BCS founding President, Prof. Sir Maurice Wilkes) using modern technology. The workshop will use the MyStorm FPGA board, a modern low-cost board for educational use. (more…)

FPGA projects past, planned and possible – London 16/2/2017

On the 16 February 2017, 18:00 – 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA,[map] (51.510812, -0.121733)

Please register to attend and share on Lanyrd.

The fifty-fifth meeting will feature a series of shorter talks that explore past, planned and possible projects which use FPGAs.

FPGA Projects – What would I build and why would I want to

PLAs have been interesting ever since the 70s when digital logic often became complex, consuming unnecessary space and power. Back then the cost of PLA deployment was high and it has continued to be high until recently. Now that we have powerful, low cost development platforms and relatively cheap FPGAs the cost equation has shifted radically.

Paul Tanner is a consultant, developer and maker in wood, metal, plastic, electronics and software. His day job is IT-based business improvement for SMEs. By night he turns energy nut, creating tools to optimise energy use. Paul graduated in electronics and was responsible for hardware and software product development and customer services in several product and service start-ups, switching to consulting in 2000.

Using FPGAs to solve realtime problems

Microcontrollers a great platform to solve basic control problems in electronics, with simple motor drivers and sensors readily avaiable and easy to integrate. However, when the motor control becomes more complex with BLDC and FOC things get much more tricky. When you have to use multiple BLDC motors and more complex sensors with image processing the poor microcontroller quickly becomes to swamped to provide control in realtime. This is where adding FPGA technology makes a great deal of sense particularly in mutli-discipline projects like robotics where many sensors, motors and image processing will need to be managed and controlled concurrently. A robotics platform must therefore contain both concurrent hardware resources, algorithmic control through soft or hard cores along with communication protocols.

Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning, inference and image processing for embedded applications using FPGA and multi-cores. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace and myStorm FPGA development boards.

FPGAs in the Cloud?

It is no secret that FPGA based computing machines are great at dealing with certain types of workloads that conventional CPU based machines can not efficiently handle. These machines, alongside their GPU and even custom ASIC based brethren, have been filling up racks in large data centres all over the globe helping speed up systems that have components of machine learning, complex analytics and even video processing.

This short talk will have a look at the state of FPGAs in the datacenter and discuss the recent developments around the availability of FPGA equipped computing nodes in commodity cloud providers.

Omer Kilic is an Embedded Systems Engineer who enjoys working with small connected computers of all shapes and sizes. He works at the various intersections of hardware and software engineering practices, product development and manufacturing.

Chip Hack 2017 & EDSAC Challenge

This talk will introduce and issue a call for participation for two events that are being hosted as part of the Wuthering Bytes technology festival, that will take place in Hebden Bridge in September, in the week following Open Source Hardware Camp 2017.

Chip Hack is a two day hands-on workshop that provides a gentle introduction to programming FPGAs and is aimed at novices with no prior experience of Hardware Description Languages (HDLs) or FPGAs. This will be followed immediately by a challenge event, during which a small team of experts will work to extend a basic functional FPGA model of EDSAC — the pioneering computer designed and constructed at Cambridge University, and which was operational by 1949.

Dr Jeremy Bennett is founder and Chief Executive of Embecosm, a consultancy implementing open source compilers and chip simulators for major corporations around the world. He is a author of the standard textbook “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003). Contact him at:

7th February update: 2 extra talks!

Deploying your FPGA toolchain consistently regardless of your development environment

With an open source tool chain for an open hardware fpga, we’re free to work in the environment of our choice. What may differ between platforms is how we put the components together, from requiring software dependences to administrative commands needed to be executed in order to build to software successfully.

pkgsrc is a cross platform packaging system which allows you to deploy open source software consistently, regardless of the environment it is operating on. This means should you desire to install the icestorm tool chain, the steps required to build or install packages is the same whether you’re running a flavour of Linux, Mac OS or Windows.

This lightning talk will introduce pkgsrc and how you can get started quickly with icestorm and other tools to help with your hardware project.

Sevan Janiyan is founder of Venture 37, which provides system administration & consultancy services. As a fan of operating systems and computers with different CPU architectures, in his spare time he maintains builds of open source software on a variety of systems featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube & OMRON LUNA-88K2 one day.

Multicore Made Simple – Conducting a Chorus of Cores on an FPGA

FPGA technology makes it simple to build a multicore CPU, by instantiating multiple copies of a soft processor design on a single chip. The challenge is to connect and coordinate the cores into a resource which is useful for application programming. While traditional multicore processors include shared memory, shared buses and/or general communications networks, all of these are costly in hardware resources and complexity, and subtle details of synchronization and cache coherency can make programming difficult and risky. Building our own system on an FPGA, we can choose a minimalist “shared nothing”
architecture, with only local memories and simple synchronous point to point communications links in a topology tailored to the application. As an example of this approach, I’ll demonstrate a 40 voice (plus
conductor) polyphonic digital audio synthesizer, running on an array of
41 Nios2 cores on an Altera Cyclone II.

Dr Richard Miller has had a long career in the borderlands between hardware and software, in academia and industry and now as an independent consultant. Particular interests have been operating systems portability (starting in 1977 with the world’s first UNIX port, from
PDP/11 to Interdata 7/32 at the University of Wollongong; and most recently porting the Plan 9 OS to the Raspberry Pi); programming language implementations in constrained environments (e.g. a LOGO interpreter on a 48KB Apple II; and a JavaCard JVM and runtime library on a smartcard with a 8KB of RAM and 1MB of flash); parallel computing infrastructure (on hardware ranging from Transputers to the Cray T3D); and embedded systems firmware (e.g. a complete Bluetooth stack for a range of prototype phones and tablets). Current work in progress includes building a communications network on an FPGA, for a microcluster of Raspberry Pi Zeroes.

Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt.

The future of Open Source: silicon chip design for the masses, musical instruments and algorithms as pictures – London 20/10/2016

This year’s BCS OSSG AGM will be held on Thursday 20th October at the BCS HQ, First Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA from 6:00pm to 8:45pm.

The AGM will be followed by four talks from our student prize winners and from the designers of MyStorm, an ultra-low cost FPGA board.

This event is free to attend for both BCS Members and non-members but?booking is required. Places are limited; please book as soon as possible.

Note: Please aim to arrive by 18:00 as the event will start at 18:15 prompt.

The timetable for the evening will be:

18:00 – Registration & refreshments
18:15 – BCS AGM and election of officers
18.45 – The Light Theremin Project
19:00 – The Next Generation of Open Source Engineers
19:15 – The use of Open Source projects to scaffold the development of new programmers
19:30 – The MyStorm project
20:00 – Sandwiches + networking
20:45 – Close